battery: li-ion 3.7v 1.369Wh
usb-c on left, from behind battery: boot, gnd, tx, rx
• Up to 16 MB Quad SPI flash
• ESP32-S3 series of SoCs embedded, Xtensa®
dual-core 32-bit LX7 microprocessor, up to 240
MHz
• 384 KB ROM
• 512 KB SRAM
• 16 KB SRAM in RTC
• Up to 8 MB PSRAM
Xtensa® Dualcore 32-bit LX7
Microproces`sor
• UART as wake-up source
UART interrupt: UART_RS485_CLASH_INT: Triggered when a collision is detected between the transmitter and the receiver
in RS485 mode.
RISC-V Coprocessor ULP: ULP-­FSM
GPIO3 controls the source of JTAG signals during the early boot process
SPI fundamentals: mosi/miso/clk/cs
4­line full­duplex 4-line here means: clock line, CS line, and two data lines. The two
data lines can be used to send or receive data simultaneousl

SPI device flash pins, single SPI
CLK IO39 32 I/O/T MTCK, GPIO39, CLK_OUT3, SUBSPICS1